The present invention relates to a channel response estimation circuit, and more particularly to a channel response estimation circuit that estimates characteristics of communication propagation paths.
In conventional channel estimation circuits, the length of a channel response to be estimated is limited to less than the length of a correlation code sequence. The channel response estimation circuit, disclosed in U.S. Pat. No. 5,623,511, will be described below by referring to FIG. 6. Referring to FIG. 6, a correlator 101 performs a convolutional operation of a correlation code sequence of an L chip length and a received signal Sr code-spread with the correlation code sequence of an L chip length and then outputs a correlator-output signal Scorri.
A shift register 601 holds the correlator-output signal Scorri of an L chip length and outputs it as a correlator-output hold signal of an L chip length. A symbol decision circuit 102 receives the correlator-output signal Scorri and subjects a symbol of L chips to a code decision and outputs it as a decision signal Sdet. A symbol delay unit 603 delays the decision signal Sdet by one symbol and outputs it as a delay decision signal Sddet1. A symbol delay unit 603 delays the delay decision signal Sddet1 by one symbol and then outputs it as a delay decision signal Sddet2.
A memory 604 outputs an inverse decision signal Sinvm corresponding to an inverse matrix which corresponds to a combination of a decision signal Sdet, a delay decision signal Sddet1, and a delay decision signal Sddet2. A correlator-output correction circuit 605 multiplies the correlator-output hold signal Shcorri of an L chip length by the inverse matrix signal Sinvm to obtain a channel response of an L chip length and then outputs it as an estimation channel signal Sestch. Thus, the channel response is estimated.
However, there is the problem that the conventional channel estimation circuit cannot estimate a channel longer than an L chip length.
The present invention is made to solve the above-mentioned problems.
Moreover, the objective of the invention is to provide a channel response estimation circuit that can estimate a channel longer than a correlation code sequence length L.
The objective of the present invention is achieved by a channel response estimation circuit, comprising a correlator for performing a convolutional operation of a received signal and a correlation code sequence to output a correlator-output signal, the received signal partially having a combination in which the correlation code sequence of an L chip length (where L is a given.natural number) and another correlation code.sequence obtained by inverting signs of the correlation code sequence are strung; a symbol decision circuit for performing a symbol decision of the correlator-output signal to output a decision signal; a pattern detection circuit for receiving the decision signal and then outputting a latch signal in response to detection of a symbol pattern of (2M+1) symbol length (where M is a given-natural number and one symbol corresponds to an L chip) in which a correlation value matrix has an inverse matrix and is used for channel response estimation; a shift register for receiving the correlator-output signal and the latch signal, holding the correlator-output signal of W chip length (where W is a natural number and is expressed as Wxe2x89xa7(L+x), where x is 0 or natural number, and xxe2x89xa6Lxc3x97(Mxe2x88x921)) when the latch signal is input, and outputting a correlator-output hold signal; an estimation range selection circuit for receiving said correlator-output hold signal and selecting a channel response range of an estimated (L+x) chip length and outputting an estimation range selection signal corresponding to the selection range; a memory for outputting an inverse matrix signal corresponding to an inverse matrix of a correlation value matrix corresponding to a symbol pattern used for channel response estimation; and a correlator-output correction circuit for receiving the correlator-output hold signal and the estimation range selection signal and obtaining a channel response of a (L+x) chip length by multiplying the inverse matrix signal by the correlator-output hold signal over a range selected by the estimation range selection signal, and thus outputting an estimation channel signal.
According to the second aspect of the present invention, a channel response estimation circuit comprises a correlator for performing a convolutional operation of a received signal and a correlation code sequence to output a correlator-output signal, the received signal partially having a combination in which the correlation code sequence of an L chip length (where L is a given natural number) and another correlation code sequence obtained by inverting signs of the correlation code sequence are strung; a symbol decision circuit for performing a symbol decision of the correlator-output signal to output a decision signal; a pattern detection circuit for receiving the decision signal and then outputting a latch signal and an inverse matrix selection signal corresponding to a symbol pattern in response to detection of one of plural symbol patterns of (2M+1) symbol length (where M is a given natural number and one symbol corresponds to an L chip) in which a correlation value matrix has an inverse matrix and is used for channel response estimation; a shift register for receiving said correlator-output signal and the latch signal, holding said correlator-output signal of W chip length (where W is a natural number and is expressed as Wxe2x89xa7(L+x), where x is 0 or natural number, and xxe2x89xa6Lxc3x97(Mxe2x88x921)) when the latch signal is input, and outputting a correlator-output hold signal; an estimation range selection circuit for receiving the correlator-output hold signal and selecting a channel response range of an estimated (L+x) chip length and outputting an estimation range selection signal corresponding to the selection range; a memory for receiving the inverse matrix selection signal and outputting an inverse matrix signal corresponding to an inverse matrix of a corresponding correlation value matrix; and a correlator-output correction circuit for receiving the correlator-output hold signal and the estimation range selection signal-and obtaining a channel response of a (L+x) chip length by multiplying the inverse matrix signal by the correlator-output hold signal over a range selected by the estimation range selection signal, and thus outputting an estimation channel signal.
According to the third aspect of the present invention, a channel response estimation circuit comprises a correlator for performing a convolutional operation of a received signal and a correlation code sequence to output a correlator-output signal, the received signal partially having a combination in which the correlation code sequence of an L chip length (where L is a given natural number) and another correlation code sequence obtained by inverting signs of the correlation code sequence are strung; a symbol decision circuit for performing a symbol decision of the correlator-output signal to output a decision signal; a pattern detection circuit for receiving the decision signal and then outputting a latch signal and a polarity selection signal in response to detection of one of two symbol patterns of (2M+1) symbol length (where M is a given natural number and one symbol corresponds to an L chip) in which a correlation-value matrix has an inverse matrix and is used for channel response estimation, the two symbol patterns having a sign opposite to each other; a shift register for receiving the correlator-output signal and the latch signal, holding the correlator-output signal of W chip length (where W is a natural number and is expressed as Wxe2x89xa7(L+x), where x is 0 or natural number, and xxe2x89xa6Lxc3x97(Mxe2x88x921)) when the latch signal is input; and outputting a correlator-output hold signal; an estimation range selection circuit for receiving the correlator-output hold signal and selecting a channel response range of an estimated (L+x) chip length and outputting an estimation range selection signal corresponding to the selection range; a memory for outputting an inverse matrix tentative signal corresponding to an inverse matrix of a correlation value matrix corresponding to a symbol pattern used for channel response estimation; a polarity selection circuit for receiving the polarity selection signal and the inverse matrix tentative signal and outputting an inverse matrix signal, obtained by inverting the sign of the inverse matrix tentative signal or the inverse matrix tentative signal, in response to the polarity selection signal; and a correlator-output correction circuit for receiving the correlator-output hold signal and the estimation range selection signal and obtaining a channel response of a (L+x) chip length by multiplying the inverse matrix signal by the correlator-output hold signal over a range selected by the estimation range selection signal and outputting an estimation channel signal.
According to the fourth aspect of.the present invention, a channel response estimation circuit comprises a correlator for performing a convolutional operation of a received signal and a correlation code sequence to output a correlator-output signal, the received signal partially having a combination in which the correlation code sequence of an L chip length (where L is a given natural number) and another correlation code sequence obtained by inverting signs of the correlation code sequence are strung; a symbol decision circuit for performing a symbol decision of said correlator-output signal to output a decision signal; a pattern detection circuit for receiving the decision signal and then outputting a latch signal and a polarity selection signal in response to detection of one of two symbol patterns of (2M+1) symbol length (where M is a given natural number and one symbol corresponds to an L chip) in which a correlation value matrix has an inverse matrix and is used for channel response estimation, the two symbol patterns having a sign opposite to each other; a shift register for receiving the correlator-output signal and the latch signal, holding the correlator-output signal of W chip length (where W is a natural number and is expressed as Wxe2x89xa7(L+x), where x is 0 or natural number, and xxe2x89xa6Lxc3x97(Mxe2x88x921)) when the latch signal is input, and outputting a correlator-output hold signal; an estimation range selection circuit for receiving the correlator-output hold signal and selecting a channel response range of an estimated (L+x) chip length and outputting an estimation range selection signal corresponding to the selection range; a memory for outputting an inverse matrix signal corresponding to an inverse matrix of a correlation value matrix corresponding to a symbol pattern used for channel response estimation; a correlator-output correction circuit for receiving the correlator-output hold signal and-the estimation range selection signal and obtaining a.tentative channel response of a (L+x) chip length by multiplying the inverse matrix signal by the correlator-output hold signal over a range selected by the estimation range selection signal, and thus outputting an estimation channel tentative signal; and a polarity selection circuit for receiving the estimation channel tentative signal and the polarity selection signal and outputting as an estimation channel signal a signal obtained by inverting the sign of the estimation channel tentative signal or the estimation channel tentative signal, in response to the.polarity selection signal.
According to the fifth aspect of the present invention, a channel response estimation circuit comprises a correlator for performing a convolutional operation of a received signal and a correlation code sequence to output a correlator-output signal, the received signal partially having a combination in which the correlation code sequence of an L chip length (where L is a given natural number) and another correlation code sequence obtained by inverting signs of the correlation code sequence are strung; a symbol decision circuit for performing a symbol decision of the correlator-output signal to output a decision signal; a pattern detection circuit for receiving the decision signal and then outputting a latch signal and a polarity selection signal and an inverse matrix selection signal corresponding to a symbol pattern when one of plural symbol patterns of (2M+1) symbol length (where M is a given natural number and one symbol corresponds to an L chip) is detected, in which a correlation value matrix has an inverse matrix and is used for channel response estimation; a shift register for receiving the correlator-output signal and the latch signal, holding the correlator-output signal of W chip length (where W is a natural number and is expressed as Wxe2x89xa7(L+x), where x is 0 or natural number, and xxe2x89xa6Lxc3x97(Mxe2x88x921)) when the latch signal is input, and outputting a correlator-output hold signal; an estimation range selection circuit for receiving the correlator-output hold signal and selecting a channel response.range of an estimated (L+x) chip length, and outputting an estimation range selection signal corresponding to the selection range; a memory for receiving the inverse matrix selection signal and outputting an inverse matrix tentative signal corresponding to an inverse matrix of a corresponding correlation value matrix; a polarity selection circuit for receiving the polarity selection signal and the inverse matrix tentative signal and outputting.as an inverse matrix signal a signal obtained by inverting the sign of the inverse matrix tentative signal or the inverse matrix tentative signal, in response to the polarity selection signal; and a correlator-output correction circuit for receiving the correlator-output hold signal and the estimation range selection signal and obtaining a channel response of a (L+x) chip length by multiplying the inverse matrix signal by the correlator-output hold signal over a range selected by the estimation range selection signal, and-outputting an estimation channel signal.
According to the sixth aspect of the present invention, a channel response estimation circuit comprises a correlator for performing a convolutional operation of a received signal and a correlation code sequence to output a correlator-output signal, the received signal partially having a combination in which the correlation code sequence of an L chip length (where L is a given natural number) and another correlation code sequence obtained by inverting signs of the correlation code sequence are strung; a symbol decision circuit for performing a symbol decision of the correlator-output signal to output a decision signal; a pattern detection circuit for receiving the decision signal and then outputting a latch signal and a polarity selection signal and a an inverse matrix selection signal corresponding to a symbol pattern, in response to one of plural symbol patterns of (2M+1) symbol length (where M is a given natural number and one symbol corresponds to an L chip), in which a correlation value matrix has an inverse matrix and is used for channel response estimation; a shift register for receiving the correlator-output signal and the latch signal, holding the correlator-output signal of W chip length (where W is a natural number and is expressed as Wxe2x89xa7(L+x), where x is 0 or natural number, and xxe2x89xa6Lxc3x97(Mxe2x88x921)) when the latch signal is input, and outputting a correlator-output hold signal; an estimation range selection circuit for receiving the correlator-output hold signal and selecting a channel response range of an estimated (L+x) chip length, and outputting an estimation range selection signal corresponding to the selection range; a memory for receiving the inverse matrix selection signal and outputting an inverse matrix signal corresponding to an inverse matrix of a corresponding correlation value matrix; a correlator-output correction circuit for receiving said correlator-output hold signal and the estimation range selection signal and obtaining a tentative channel response of a (L+x) chip length by multiplying the inverse matrix signal by the correlator-output hold signal over-a range selected by the estimation range selection signal, and outputting an estimation channel tentative signal; and a polarity selection circuit for receiving the estimation channel tentative signal and the polarity selection signal and outputting as an estimation channel signal a signal obtained by inverting the sign of the estimation channel tentative signal or the estimation channel tentative signal, in response to the polarity selection signal.
According to the present invention with above-mentioned configuration, the pattern detection circuit detects a symbol pattern corresponding to the channel length to be estimated and the estimation range.selection circuit selects the range of a channel response to be estimated. Thus, a channel longer than the length L of a correlation code sequence can be estimated.